Generally, in high speed circuit implemented by a high frequency, a differential circuit is mainly used to improve the noise characteristics thereof. Among them, especially in the circuit implemented by a high frequency more than several ten MHz, since a signal voltage level is below 1 V, circuits which are enabled by a differential ECL signal(high level: 0 V, low level: -1 V) or differential PECL signal(high level: +4 V, low level: +3 V) having a high speed operational characteristic are widely used. An integrated circuit for ECL or PECL signal process utilizing the high speed circuits as mentioned above is mainly for use with other circuits or other systems and is connected with impedance matching of 50 Ohms at input/output stages. Thus, a buffer circuit provided at the output stage of the integrated circuit which is implemented by the high frequency should have a capability of operating a load having 50 Ohms of load resistance.
FIG. 1 illustrates a circuit showing a conventional CMOS differential output buffer and load resistors each connected thereto.
In the figure, the circuit comprises two input stages 1 and 2 to which signals having a complementary relation with the ECL signal or THE PECL signal are applied, respectively. Reference numerals 3 and 4 denote first and second PMOS transistors, reference numerals 5 and 6 denote first and second pads to output output signals, and reference numerals 7 and 8 denote first and second load resistors each having 50 ohms, assuming when the circuit is in use.
A constant current source CS1 is connected to the voltage source Vdd (+5 V) and is also connected to the respective drains of the first and the second PMOS transistors 3 and 4. The respective gates of the first and the second PMOS transistors 3 and 4 are connected to the first and input stages 1 and 2, and the respective sources thereof are connected to the first and the second pads 5 and 6, respectively. The first and the second resistors 7 and 8 are then connected between a voltage source Vtt (+3 V) and the first and the second pads 5 and 6, respectively.
The operational principle of the circuit as constituted above will now be described in detail.
Referring again to FIG. 1, when a high level voltage (+4 V) is applied to the first input stage 1, and a low level voltage (+3 V) is applied to the second input stage 2,, respectively, the second PMOS transistor 4 turns on, allowing 20 mA of current to flow from the second pad 6 to the second load resistor 8. Thus, 1 V of potential difference between the first and the second load resistors 7 and 8 occurs, so that the first output pad 5 will be maintained at a low level voltage (+3 V), whereas the second output pad 6 will be maintained at a high level voltage (+4 V), respectively.
On the contrary, if a low level voltage (+3 V) is applied to the first input stage 1, and a high level voltage (+4 V) is applied to the second input stage 2, respectively, the first PMOS transistor 3 turns on, thereby permitting 20 mA of current to flow from the first pad 6 to the first load resistor 7. As a result, the first output pad 5 may be maintained at a high level voltage (+4 V), whereas the second output pad 6 may then be maintained at a low level voltage (+3 V), respectively. Likewise, 1 V of potential difference between the first and the second load resistors 7 and 8 occurs. Considering an operational point of view of the entire output buffer, in order to obtain 1 V of potential difference at the first and the second output pads 5 and 6, it is necessary for the output buffer to have a capability of providing 20 mA in total. As a result, the total power consumption required for the entire circuit including the PMOS transistors and load resistors will be about 100 mW.
Therefore, it is an object of the present invention to overcome the above disadvantages in the prior art and provide a differential output buffer for Emitter Coupled Logic(ECL) signal or Pseudo ECL(PECL) signal having a low power consumption and, superior high frequency characteristics.
The preceding objects should be construed as merely presenting a few of the more pertinent features and applications of the invention. Many other beneficial results can be obtained by applying the disclosed invention in a different manner or modifying the invention within the scope of the disclosure. Accordingly, other objects and a fuller understanding of the invention may be had by referring to both the summary of the invention and the detailed description, below, which describe the preferred embodiment in addition to the scope of the invention defined by the claims considered in conjunction with the accompanying drawings.